GE CM6 Hardware Reference Manual page 63

LED
GE Intelligent Platforms – CM6 Hardware Reference Manual, Fourth Edition
Digital Switch
The CM6 has a digital switch for select and hold reset configurations. This
digital switch is a Maxim DS3905 "Triple 128-Position Nonvolatile Digital
Variable Resistor/Switch". The settings of the digital switches are controlled by
the boot loader.
Digital switch output 0 controls the "Core 1 Low Memory Offset Mode" which
provides the capability for access to the lowest 256Mbyte of real addresses
from core 1 to be offset in order to provide each core a unique and private
address space in actual memory. The feature is used for Asymmetric Multi
Processor (ASMP) operating systems.
Output 0: open
set to 1kΩ
Digital switch output 1 controls the "Core 1 Enable" option
which allows the user to enable or disable the second core (if available) during
power-on reset.
Output 1: open
set to 1kΩ
Digital switch output 2 is not used
There is one status LED at the CM6 available and a status signal (BFAIL#) at
the rear which is designated as an external "Board Fail" LED.
BFAIL# (cPCI J2 pin E19) is an open drain signal to source a LED at 3.3 V
with 4 mA. The CM6 has an active low board fail signal (BFAIL#) at J2. The
signal is active after reset and may set inactive after BIT test. The user may
connect a red LED at the signal and if the LED is off this indicate a successful
BIT test. BFAIL# is controlled with the CPLD Control Register (CR) Bit 6.
Table 22: Rear I/O LED indication
Status
Power-up
OS boot
User
The Boot and Status LED (see table 23) is a green/red bi-color LED located at
the board for boot up status indication. After boot loading the user software is
free to use this LED for any purpose. The red and green of the bi-color LED is
controlled at the CPLD Control Register (CR) Bit 4 and bit 5.
- no extra translation performed
- extra 256 MByte translation
- Core 1 enabled
- Core 1 disabled
BFAIL#
default low
see programming manual
Low or High
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