GE CM6 Hardware Reference Manual page 57

Memory Controller
Flash Memory
GE Intelligent Platforms – CM6 Hardware Reference Manual, Fourth Edition
The CM6 uses only one of the two memory controllers in the MPC8641. CM6
supports double data rate 2 synchronous DRAM (DDR2 SDRAM) up to a
clock rate of 333 MHz (data rate of 667MHz) and a data bus width of 64 bits,
this is equivalent to the PC2-5300 specification (5.3Gbyte/s bandwidth).
Memory speed depends on used MPC8641 version and environment
requirements, please contact factory. One soldered bank is provided by the
CM6 with a size of either 512 MByte, 1Gbyte, or 2Gbyte (future). A built-in 8-
bit wide error correction code (ECC) ensures the data integrity of the memory
bank.
The CM6 provides one bank of 128MB or 256Mbyte soldered flash ROM. The
flash devices are located on Local Bus Controller of the MPC8641 with a 32bit
wide data bus. The flash memory holds the boot loader of the CM6 and
optional the application software.
Flash Write Protection
Operating software can write and erase data from the flash devices. Each flash
device provides 'chip erase' functions as well separate erase and protection of
sectors. The CM6 provides several write-protect mechanism to prevent code
data loss during power cycling and system initialization.
External Write Protection
The HW_WP# signal at the backplane (J2 pin E21) prevents any write to the
flash ROM.
If the HW_WP# signal is asserted (active low) all write commands to the Flash
devices are disabled. That means even the command, "Read Device Code" is
inhibited.
The state of HW_WP# can be read in the CPLD Configuration Register.
Device Write Protect
Inside the MPC8641 Local Bus Controller register set the according chip select
(LCS1) of the Flash Device may set to write protect.
Boot Code Selection
The SW_CFG# signal provided at the backplane (cPCI J2 pin D21) selects
which boot code is executed on power-up or reset. If SW_CFG# is inactive
(high) the code in the user boot ROM is executed, provided that a boot
description header with a valid checksum is detected. If SW_CFG# is active
(low) an emergency boot code is executed.
Flash Kill Option
For security reasons the flash devices can be destroyed with this optional
feature. If signal FKILL# (cPCI J2 pin A15) is tied to ground the flash devices
are supplied with +12 V instead +3.3 V. This over voltage will destroy the
devices and its content. In inactive state the signal FKILL# has a high level of
+12 V that means an output which drives FKILL# must withstand a high level
of +12V. The feature is only usable if the CM6 is supplied with +12 V power
rail. Besides the flash devices other logic may be damaged if a Flash Kill is
performed!
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