Table of Contents
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Program Control (Branch) 4-10, 8-20
Shift and Rotate 4-9, 8-19
Single Operand 8-18
System Control 4-11, 8-21
Table Lookup and Interpolation 4-188
Interrupts 6-12
–L–
Logic Instructions 4-8
Low-Power Stop (LPSTOP) 4-1, 5-1
–M–
M68000 Family Addressing Capability 3-14
M68000 Family Compatibility 4-1
Memory
Addressing Modes 3-4
Indirect Addressing 3-4
Organization 2-6
Virtual 1-2
Microbus Controller 8-3
Microsequencer 8-1
Model, Programming 2-1
Move Instruction Timing 8-14
Move Instruction, Special Purpose, Timing 8-14
Multiple Exceptions 6-4
–N–
Negative Tails 8-6
Organization in Memory 2-6
Normal Processing State 5-1
Notation Conventions, Addressing 3-2
Notation, Instruction Set 4-3
–O–
Opcode Tracking during Loop Mode 7-27
Opcode Tracking in Background Mode 7-2, 7-25
Organization
Memory 2-6
Registers 2-4
Overlap 8-4
–P–
Pipeline Sync with the NOP Instruction 4-194
Prefetch Controller 8-3
CPU32
REFERENCE MANUAL
Priority
Exception 6-4
Interrupt 6-12
Privilege Levels 5-1
Changing 5-2
Supervisor 5-2
User 5-2
Privilege Violations 6-10
Processing of Specific Exceptions 6-5
Processing States 5-1
Program and Data References 3-1, 5-3
Program Control (Branch) Instructions 4-10
Program Counter Indirect with Displacement Mode 3-7
Index (8-Bit Displacement) 3-7, 3-8
Index (Base Displacement) 3-8
Programming Model 2-1
Programming View of Addressing Modes 3-11
Queues 3-17
References
Data 3-1
Implicit 3-2
Program 3-1
Register Direct Mode 3-3
Registers
Address 2-5
Condition Code 2-3, 4-5
Control 2-5
Data 2-4
Function Code 2-3
Organization 2-2
Status 2-3
Vector Base 2-3, 6-1
Released Writes 6-16, 6-19
Reset 6-5
Resource Scheduling 8-1
Return from Exception 6-13
Rotate Instructions 4-9
Save and Restore Operation Timing 8-22
Serial Interface (BDM) 7-7
Shift and Rotate Instruction Timing 8-19
Shift and Rotate Instructions 4-9
INDEX
–Q–
–R–
–S–
MOTOROLA
I-3
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