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When the aborted bus cycle is an instruction prefetch, the processor will not initiate
exception processing unless the prefetched information is used. For example, if a
branch instruction flushes an aborted prefetch, that word is not accessed, and no ex-
ception occurs.
When the aborted bus cycle is a data access, the processor initiates exception pro-
cessing immediately, except in the case of released operand writes. Released write
bus errors are delayed until the next instruction boundary or until another operand ac-
cess is attempted.
Exception processing for bus error exceptions follows the regular sequence, but con-
text preservation is more involved than for other exceptions because a bus exception
can be initiated while an instruction is executing. Several bus error stack format orga-
nizations are utilized to provide additional information regarding the nature of the fault.
First, any register altered by a faulted-instruction effective address calculation is re-
stored to its initial value. Then a special status word (SSW) is placed on the stack. The
SSW contains specific Information about the aborted access — size, type of access
(read or write), bus cycle type, and function code are saved. Finally, fault address, bus
error exception vector number, program counter value, and a copy of the status regis-
ter are saved.
If a bus error occurs during exception processing for a bus error, an address error, a
reset, or while the processor is loading stack information during RTE execution, the
processor halts. This simplifies isolation of catastrophic system failure by preventing
processor interaction with stacks and memory. Only assertion of RESET can restart a
halted processor.
6.2.3 Address Error
Address error exceptions occur when the processor attempts to access an instruction,
word operand, or long-word operand at an odd address. The effect is much the same
as an internally generated bus error. The exception processing sequence is the same
as that for bus error, except that the vector number refers to the address error excep-
tion vector.
Address error exception processing begins when the processor attempts to use infor-
mation from the aborted bus cycle.
If the aborted cycle is a data space access, exception processing begins when the pro-
cessor attempts to use the data, except in the case of a released operand write. Re-
leased write exceptions are delayed until the next instruction boundary or attempted
operand access.
An address exception on a branch to an odd address is delayed until the program
counter is changed. No exception occurs if the branch is not taken. In this case, the
fault address and return program counter value placed in the exception stack frame
are the odd address, and the current instruction program counter points to the instruc-
tion that caused the exception.
CPU32
REFERENCE MANUAL
EXCEPTION PROCESSING
MOTOROLA
6-7
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