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LSL, LSR (Register)
15
14
13
1
1
1
Count/Register Field:
If I/R Field = 0, Specifies Shift Count
If I/R Field = 1, Specifies Data Register that contains Shift Count
dr Field: 0 = Right 1 = Left
Size Field: 00 = Byte 01 = Word 10 = Long
I/R Field: 0 = Immediate Shift Count 1 = Register Shift Count
ROXL, ROXR (Register)
15
14
13
1
1
1
Count/Register Field:
If I/R Field = 0, Specifies Shift Count
If I/R Field = 1, Specifies Data Register that contains Shift Count
dr Field: 0 = Right 1 = Left
Size Field: 00 = Byte 01 = Word 10 = Long
I/R Field: 0 = Immediate Shift Count 1 = Register Shift Count
ROL, ROR
15
14
13
1
1
1
Count/Register Field:
If I/R Field = 0, Specifies Shift Count
If I/R Field = 1, Specifies Data Register that contains Shift Count
dr Field: 0 = Right 1 = Left
Size Field: 00 = Byte 01 = Word 10 = Long
I/R Field: 0 = Immediate Shift Count 1 = Register Shift Count
ASL, ASR (Memory)
15
14
13
1
1
1
dr Field: 0 = Right 1 = Left
LSL, LSR (Memory)
15
14
13
1
1
1
dr Field: 0 = Right 1 = Left
MOTOROLA
4-186
12
11
10
9
0
COUNT/REGISTER
12
11
10
9
0
COUNT/REGISTER
12
11
10
9
0
COUNT/REGISTER
12
11
10
9
0
0
0
0
12
11
10
9
0
0
0
1
INSTRUCTION SET
8
7
6
5
dr
SIZE
i/r
8
7
6
5
dr
SIZE
i/r
8
7
6
5
dr
SIZE
i/r
8
7
6
5
dr
1
1
8
7
6
5
dr
1
1
4
3
2
1
0
1
REGISTER
4
3
2
1
1
0
REGISTER
4
3
2
1
1
1
REGISTER
4
3
2
1
EFFECTIVE ADDRESS
MODE
REGISTER
4
3
2
1
EFFECTIVE ADDRESS
MODE
REGISTER
REFERENCE MANUAL
0
0
0
0
0
CPU32
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