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Bus operation in progress at the time of a fault is conveyed by the SSW.
15
14
13
TP
MV
0
TR
The BERR stack frame is 12 words in length. There are three variations of the frame,
each distinguished by different values in the SSW TP and MV fields.
An internal transfer count register appears at location SP + 14 in all bus error stack
frames. The register contains an 8-bit microcode revision number, and, for type III
faults, an 8-bit transfer count. Register format is shown in Figure 6-5.
15
MICROCODE REVISION NUMBER
The microcode revision number is checked before a BERR stack frame is restored via
RTE. In a multiprocessor system, this check insures that a processor using stacked
information is at the same revision level as the processor that created it.
The transfer count is ignored unless the MV bit in the stacked SSW is set. If the MV bit
is set, the least significant byte of the internal register is reloaded into the MOVEM
transfer counter during RTE execution.
For faults occurring during normal instruction execution (both prefetches and non-
MOVEM operand accesses) SSW [TP:MV] = 00. Stack frame format is shown in Fig-
ure 6-6.
Faults that occur during the operand portion of the MOVEM instruction.are identified
by SSW [TP:MV] = 01. Stack frame format is shown in Figure 6-7.
When a bus error occurs during exception processing, SSW [TP:MV] = 10. The frame
shown in Figure 6-8 is written below the faulting frame. Stacking begins at the address
pointed to by SP – 6 (SP value is the value before initial stacking on the faulted frame).
The frame can have either four or six words, depending on the type of error. Four word
stack frames do not include the faulted instruction program counter (the internal trans-
fer count register is located at SP + $10 and the SSW is located at SP + $12).
The fault address of a dynamically sized bus cycle is the address of the upper byte,
regardless of the byte that caused the error.
CPU32
REFERENCE MANUAL
12
11
10
9
B1
B0
RR
Figure 6-5 Internal Transfer Count Register
EXCEPTION PROCESSING
8
7
6
5
RM
IN
RW
LG
8
7
4
3
2
1
SIZ
FUNC
TRANSFER COUNT
MOTOROLA
0
0
6-23
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