On-Chip Hardware Breakpoint Overview - Motorola CPU32 Reference Manual

7.1.3 On-Chip Hardware Breakpoint Overview

An external breakpoint input and an on-chip hardware breakpoint capability permit
breakpoint trap on any memory access. Off-chip address comparators preclude break-
points on internal accesses unless show cycles are enabled. Breakpoints on
prefetched instructions, which are flushed from the pipeline before execution, are not
acknowledged, but operand breakpoints are always acknowledged. Acknowledged
breakpoints can initiate either exception processing or background debug mode
(BDM). See 6.2.6 Hardware Breakpoints for more information.
7.2 Background Debug Mode (BDM)
BDM is an alternate CPU32 operating mode. During BDM, normal instruction execu-
tion is suspended, and special microcode performs debugging functions under exter-
nal control. Figure 7-3 is a BDM block diagram.
MICROCODE
EXECUTION
UNIT
BDM can be initiated in several ways — by externally generated breakpoints, by inter-
nal peripheral breakpoints, by the background (BGND) instruction, or by catastrophic
exception conditions. While in BDM, the CPU32 ceases to fetch instructions via the
parallel bus and communicates with the development system via a dedicated, high-
speed, SPI-type serial command interface.
CPU32
REFERENCE MANUAL
SERIAL
INTERFACE
SEQUENCER
IRC IRB
BERR BERR BERR
BKPT BKPT BKPT
Figure 7-3 BDM Block Diagram
DEVELOPMENT SUPPORT
IRA
BUS
CONTROL
IPIPE/DSO
IFETCH/DSI
BKPT/DSCLK
DATA BUS
BERR
FREEZE
ADDRESS BUS
MOTOROLA
7-3