Figure 9-1 Triple Timer Module Block Diagram - Motorola DSP56309 User Manual

Triple Timer Module
Triple Timer Module Architecture
GDB
24
TPLR
Timer Prescaler
Load Register
21-bit Counter
CLK/2 TIO0 TIO1 TIO2
9.2.2 Timer Block Diagram
The timer block diagram (in Figure 9-2) shows the structure of a timer module. The
timer programmerÕs model (in Figure 9-3 on page 9-6) shows the structure of the timer
registers. The three timers are identical in structure and function. A generic timer is
discussed in this section.
The timer includes a 24-bit counter, a 24-bit read/write timer control and status register
(TCSR), a 24-bit read-only timer count register (TCR), a 24-bit write-only timer load
register (TLR), a 24-bit read/write timer compare register (TCPR), and logic for clock
selection and interrupt/DMA trigger generation.
The timer mode is controlled by the TC[3:0] bits of the timer control/status register
(TCSR). For a listing of the timer modes, see Section 9ÑTimer Operational Modes. For
a description of their operation, see Section 9.4.1ÑTiming Modes.
9-4
24
TPCR
Timer Prescaler
Count Register

Figure 9-1 Triple Timer Module Block Diagram

DSP56309UM/D
24
Timer 0
Timer 1
Timer 2
24
AA0673
MOTOROLA