Motorola DSP56309 User Manual page 223

Serial Communication Interface (SCI)
SCI Programming Model
polled to determine if the receive data register is full. If both RIE and RDRF are set, the
SCI requests an SCI receive data interrupt from the interrupt controller.
Receive interrupts with exception have higher priority than normal receive data
interrupts. Therefore, if an exception occurs (i.e., if PE, FE, or OR are set) and REIE is set,
the SCI requests an SCI receive data with exception interrupt from the interrupt
controller. Either a hardware RESET signal or a software RESET instruction clears RIE.
8.3.1.11 SCR SCI Transmit Interrupt Enable (TIE) Bit 12
The TIE bit is set to enable the SCI transmit data interrupt. If TIE is cleared, transmit data
interrupts are disabled, and the transmit data register empty (TDRE) bit in the SCI status
register must be polled to determine if the transmit data register is empty. If both TIE
and TDRE are set, the SCI requests an SCI transmit data interrupt from the interrupt
controller. Either a hardware RESET signal or a software RESET instruction clears TIE.
8.3.1.12 SCR Timer Interrupt Enable (TMIE) Bit 13
The TMIE bit is set to enable the SCI timer interrupt. If TMIE is set, timer interrupt
requests are sent to the interrupt controller at the rate set by the SCI clock register. The
timer interrupt is automatically cleared by the timer interrupt acknowledge from the
interrupt controller. This feature allows DSP programmers to use the SCI baud rate
generator as a simple periodic interrupt generator if the SCI is not in use, if external
clocks are used for the SCI, or if periodic interrupts are needed at the SCI baud rate. The
SCI internal clock is divided by 16 (to match the 1
generation. This timer does not require that any SCI signals be configured for SCI use to
operate. Either a hardware RESET signal or a software RESET instruction clears TMIE.
8.3.1.13 SCR Timer Interrupt Rate (STIR) Bit 14
The STIR bit controls a divide-by-32 in the SCI Timer interrupt generator. When STIR is
cleared, the divide-by-32 is inserted in the chain. When STIR is set, the divide-by-32 is
bypassed, thereby increasing timer resolution by a factor of 32. Either a hardware RESET
signal or a software RESET instruction clears this bit. To insure proper operation of the
timer, STIR must not be changed during timer operation (i.e., if TMIE = 1).
8.3.1.14 SCR SCI Clock Polarity (SCKP) Bit 15
The SCKP bit controls the clock polarity sourced or received on the clock signal (SCLK),
eliminating the need for an external inverter. When SCKP is cleared, the clock polarity is
positive. When SCKP is set, the clock polarity is negative. In synchronous mode, positive
polarity means that the clock is normally positive and transitions negative during valid
data. Negative polarity means that the clock is normally negative and transitions
positive during valid data. In asynchronous mode, positive polarity means that the
rising edge of the clock occurs in the center of the period that data is valid. Negative
polarity means that the falling edge of the clock occurs during the center of the period
8-12
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SCI baud rate) for timer interrupt
DSP56309UM/D MOTOROLA