Table 11-1 Jtag Instructions - Motorola DSP56309 User Manual

JTAG Port
TAP Controller
B3
0
0
0
0
0
0
0
0
1
1
1
1
The parallel output of the instruction register is reset to 0010 in the Test-Logic-Reset
controller state, which is equivalent to the IDCODE instruction.
During the Capture-IR controller state, the parallel inputs to the instruction shift register
are loaded with 01 in the LSBs as required by the standard. The two MSBs are loaded
with the values of the core status bits OS1 and OS0 from the OnCE controller. See
Section 10ÑOn-Chip Emulation Module for a description of the status bits.
11.3.2.1 EXTEST (B[3:0] = 0000)
The external test (EXTEST) instruction selects the BSR. EXTEST also asserts internal reset
for the DSP56300 core system logic to force a predictable internal state while performing
external boundary scan operations.
By using the TAP, the BSR is capable of the following:
¥ Scanning user-defined values into the output buffers
¥ Capturing values presented to input signals
11-8

Table 11-1 JTAG Instructions

Code
B2 B1 B0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 x
1 0
1 1
1 1
DSP56309UM/D
Instruction
0 EXTEST
1 SAMPLE/PRELOAD
0 IDCODE
1 CLAMP
0 HI-Z
1 RESERVED
0 ENABLE_ONCE
1 DEBUG_REQUEST
x RESERVED
x RESERVED
0 RESERVED
1 BYPASS
MOTOROLA