Motorola DSP56309 User Manual page 224

that data is valid. Either a hardware RESET signal or a software RESET instruction clears
SCKP.
8.3.1.15 Receive with Exception Interrupt Enable (REIE) Bit 16
The REIE bit is set to enable the SCI receive data with exception interrupt. If REIE is
cleared, the receive data with exception interrupt is disabled. If both REIE and RDRF are
set, and PE, FE, and OR are not all cleared, the SCI requests an SCI receive data with
exception interrupt from the interrupt controller. Either a hardware RESET signal or a
software RESET instruction clears REIE.
8.3.2 SCI Status Register (SSR)
The SSR is a 24-bit, read-only register used by the DSP to determine the status of the SCI.
The status bits are described in the following paragraphs.
8.3.2.1 SSR Transmitter Empty (TRNE) Bit 0
The TRNE flag bit is set when both the transmit shift register and transmit data register
(STX) are empty to indicate that there is no data in the transmitter. When TRNE is set,
data written to one of the three STX locations or to the transmit data address register
(STXA) is transferred to the transmit shift register and is the first data transmitted. TRNE
is cleared when TDRE is cleared by writing data into the STX or the STXA, or when an
idle, preamble, or break is transmitted. This bit, when set, indicates that the transmitter
is empty; therefore, the data written to STX or STXA is transmitted next. That is, there is
no word in the transmit shift register presently being transmitted. This procedure is
useful when initiating the transfer of a message (i.e., a string of characters). TRNE is set
by a hardware RESET signal, software RESET instruction, SCI individual reset, or STOP
instruction.
8.3.2.2 SSR Transmit Data Register Empty (TDRE) Bit 1
The TDRE flag bit is set when the SCI transmit data register is empty. When TDRE is set,
new data can be written to one of the SCI transmit data registers (STX) or the transmit
data address register (STXA). TDRE is cleared when the SCI transmit data register is
written. TDRE is set by the hardware RESET signal, software RESET instruction, SCI
individual reset, or STOP instruction.
In synchronous mode, when using the internal SCI clock, there is a delay of up to 5.5
serial clock cycles between the time that STX is written until TDRE is set, indicating the
data has been transferred from the STX to the transmit shift register. There is a 2 to
4 serial clock cycle delay between writing STX and loading the transmit shift register; in
addition, TDRE is set in the middle of transmitting the second bit. When using an
external serial transmit clock, if the clock stops, the SCI transmitter stops. TDRE is not set
MOTOROLA
Serial Communication Interface (SCI)
DSP56309UM/D
SCI Programming Model
8-13