Table 7-3 Fsl1 And Fsl0 Encoding - Motorola DSP56309 User Manual

7.4.2.6 CRB Shift Direction (SHFD) Bit 6
The setting of the SHFD bit determines the shift direction of the transmit or receive shift
register. If SHFD is set, data is shifted out with the LSB first. If SHFD is cleared, data is
shifted out MSB first; see Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32.
Received data is shifted in LSB first when SHFD is set or MSB first when SHFD is
cleared.
Either a hardware RESET signal or a software RESET instruction clears SHFD.
7.4.2.7 CRB Frame Sync Length FSL[1:0] Bits 7 and 8
These bits select the length of frame sync to be generated or recognized; see Figure 7-11
on page 7-19, Figure 7-14 on page 7-22, and Figure 7-15 on page 7-23. The values of
FSL[1:0] are documented in Table 7-3.
The word length is defined by WL[2:0].
Either a hardware RESET signal or a software RESET instruction clears FSL[1:0].
7.4.2.8 CRB Frame Sync Relative Timing (FSR) Bit 9
The FSR bit determines the relative timing of the receive and transmit frame sync signal
in reference to the serial data lines, for word length frame sync only. When FSR is
cleared, the word length frame sync occurs together with the first bit of the data word of
the first slot. When FSR is set, the word length frame sync occurs one serial clock cycle
earlier (i.e., simultaneously with the last bit of the previous data word).
Either a hardware RESET signal or a software RESET instruction clears FSR.
7.4.2.9 CRB Frame Sync Polarity (FSP) Bit 10
The FSP bit determines the polarity of the receive and transmit frame sync signals. When
FSP is cleared, the frame sync signal polarity is positive (i.e., the frame start is indicated
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)

Table 7-3 FSL1 and FSL0 Encoding

FSL1 FSL0
0 0
0 1
1 0
1 1
DSP56309UM/D
ESSI Programming Model
Frame Sync Length
RX TX
word word
word bit
bit bit
bit word
7-17