Figure 1-1 Dsp56009 Block Diagram - Motorola DSP56009 User Manual

General
Purpose
I/O
(GPIO)
24-Bit
DSP56000
Core
Internal
Data
Bus
Switch
TM
OnCE Port
Clock
PLL
Gen.
3 4
IRQA, IRQB
NMI, RESET
The DSP56000 core is dual-natured in that there are two independent, expandable
data memory spaces, two address arithmetic units, and a Data ALU that has two
accumulators and two shifter/limiters. The duality of the architecture makes it easier
to write software for DSP applications. For example, data is naturally partitioned into
coefficient and data spaces for filtering and transformations, and into real and
imaginary spaces for performing complex arithmetic.
The DSP56000 architecture is especially suited for audio applications since its
arithmetic operations are executed on 24-bit or 48-bit data words. This is a significant
advantage for audio over 16-bit and 32-bit architectures: 16-bit DSP architectures
have insufficient precision for CD-quality sound, and while 32-bit DSP architectures
possess the necessary precision, with extra silicon and cost overhead they are not
suitable for high-volume, cost-driven audio applications.
MOTOROLA
4 5
9
Serial Serial
Audio Host
Interface Interface
(SAI) (SHI)
Address
Generation
Unit
GDB
PDB
XDB
YDB
Program
Interrupt
Decode
Control
Controller
Program Control Unit
4

Figure 1-1 DSP56009 Block Diagram

DSP56009 User's Manual
DSP56009 Architectural Overview
29
External
Program
Memory
Memory
Interface
(EMI)
PAB
XAB
YAB
Program
Address
24 × 24 + 56 → 56-Bit MAC
Generator
Two 56-Bit Accumulators
Overview
16-Bit Bus
24-Bit Bus
X Data Y Data
Memory Memory
Data ALU
AA0248k
1-9