Figure 8-5 16 X Serial Clock - Motorola DSP56309 User Manual

Serial Communication Interface (SCI)
SCI Programming Model
¥ For asynchronous mode, the output clock is continuous.
¥ For synchronous mode, a 1
maximum 1
¥ For synchronous mode, the clock is gated.
¥ For synchronous mode, the transmitter and receiver are synchronous with each
other.
Idle Line
RX, TX Data
(SSFTD = 0)
x1 Clock
x16 Clock
(SCKP = 0)
8.3.3.1 SCCR Clock Divider (CD[11:0]) Bits 11Ð0
The CD[11:0] bits specify the divide ratio of the prescale divider in the SCI clock
generator. A divide ratio from 1 to 4096 (CD[11:0] = $000 to $FFF) can be selected. Either
a hardware RESET signal or a software RESET instruction clears CD11ÐCD0.
8.3.3.2 SCCR Clock Out Divider (COD) Bit 12
The clock output divider is controlled by COD and SCI mode. If SCI mode is
synchronous, the output divider is fixed at divide by 2.
If SCI mode is asynchronous, then one of the following conditions occurs:
¥ If COD is cleared and SCLK is an output (i.e., TCM and RCM are both cleared),
the SCI clock is divided by 16 before being output to the SCLK signal. Thus, the
SCLK output is a 1
¥ If COD is set and SCLK is an output, the SCI clock is fed directly out to the SCLK
signal. Thus, the SCLK output is a 16
Either a hardware RESET signal or a software RESET instruction clears COD.
8-16
´
clock is used for the output or input baud rate. The
´
clock is the crystal frequency divided by 8.
0 1
Start

Figure 8-5 16 x Serial Clock

´
clock.
DSP56309UM/D
Select 8-or 9-bit Words
2 3 4 5 6
´
baud clock.
7 8
Stop Start
AA0692
MOTOROLA