Phase-Locked Loop (Pll); Table 2-5 Phase-Locked Loop Signals - Motorola DSP56309 User Manual

Signal/Connection Descriptions

Phase-Locked Loop (PLL)

Signal
Type
Name
XTAL Output
2.5

PHASE-LOCKED LOOP (PLL)

Phase-locked loop signal descriptions are listed in Table 2-5.
Signal
Type
Name
PCAP Input
CLKOUT Output
2-8
Table 2-4 Clock Signals (Continued)
State
During
Reset
Chip-driven Crystal OutputÑXTAL connects the internal crystal
oscillator output to an external crystal. If an external
clock is used, leave XTAL unconnected.

Table 2-5 Phase-Locked Loop Signals

State During
Reset
Input PLL CapacitorÑPCAP is an input connecting an
off-chip capacitor to the PLL filter. Connect one
capacitor terminal to PCAP and the other terminal
to V
If the PLL is not used, PCAP can be tied to V
tied to GND, or left floating.
Chip-driven Clock OutputÑCLKOUT provides an output
clock synchronized to the internal core clock
phase.
If the PLL is enabled and both the multiplication
and division factors equal one, then CLKOUT is
also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is
half the frequency of EXTAL.
DSP56309UM/D
Signal Description
Signal Description
.
CCP
,
CC
MOTOROLA