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SECTION 3
DATA ORGANIZATION AND
ADDRESSING CAPABILITIES
The addressing mode of an instruction can specify the value of an operand (an
immediate operand), a register that contains the operand (register direct
addressing mode), or how the effective address of an operand in memory is
III
derived. An assembler syntax has been defined for each addressing mode.
Figure 3-1 shows the general format of the single-effective-address instruction
operation word. The effective address field specifies the addressing mode for
an operand that can use one of the numerous defined modes. The designation
is composed of two 3-bit fields, the mode field and the register field. The value
in the mode field selects a mode or a set of modes. The register field specifies a
register for the mode or a submode for modes that do not use registers.
15
14
13
12
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10
9
8
7
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5
4
3
2
a
EFFECTIVE ADDRESS
X
X
X
X
X
X
X
X
X
X
MODE
I
REGISTER
Figure 3-1. Single-Effective-Address Instruction Operation Word
Many instructions imply the addressing mode for only one of the operands. The
formats of these instructions include appropriate fields for operands that use
only a single addressing mode.
Additional information may be needed to specify an operand address. This
information is contained in an additional word or words called the effective
address extension, and is considered part of an instruction. Address extension
formats are discussed in 3.4.4 Effective Address Encoding Summary.
When an addressing mode uses a register, the register is specified by the
register field of the operation word. Other fields within the instruction specify
whether the selected register is an address or data register and how the register
is to be used.
CPU32 REFERENCE MANUAL
DATA ORGANIZATION AND
ADDRESSING
CAPABILITIES
MOTOROLA
3-1
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