Motorola CPU32 Reference Manual page 95

M68300 series central processor unit
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II
BCHG
Operation:
Assembler
Syntax:
Attributes:
Test a Bit and Change
«number) of Destination)
=>
Z;
«number) of Destination)
=>
(bit number) of Destination
BCHG Dn, (ea)
BCHG #(data), (ea)
Size
=
(Byte, Long)
BCHG
Descriptio n:
Tests a specified bit in the destination operand, sets the Z condition code
appropriately, then inverts the specified bit. When the destination is a data register, any of the 32
bits can be specified by the modulo 32 bit number. When the destination is a memory location,
the operation is a byte operation, and the bit number is modulo 8. In all cases, bit zero refers to the
least significant bit. The bit number for this operation may be specified in either of two ways:
1. Immediate - The bit number is specified by a second instruction word
2. Register - The specified data register contains the bit number.
Condition Codes:
X
N
X Not affected
N Not affected
z
v
C
Z Set if the bit tested is zero. Cleared otherwise
V Not affected
C Not affected
Instruction Format (Bit Number StatiC, specified as Immediate data):
15
14
13
12
11
10
9
8
7
6
5
4
3
2
EFFECTIVE ADDRESS
0
0
0
0
1
0
0
0
0
1
I
MODE
REGISTER
0
0
0
0
0
0
0
0
BIT NUMBER
o
MOTOROLA
4-42
INSTRUCTION SET
CPU32 REFERENCE MANUAL

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