Shift And Rotate Instructions - Motorola CPU32 Reference Manual

4.3.4 Logic Instructions
The logical operation instructions (AND, OR, EOR, and NOT) perform logical
operations with all sizes of integer data operands. A similar set of immediate
instructions (ANDI, ORI, and EORI) provide these logical operations with all
sizes of immediate data. The TST instruction arithmetically compares the
operand with zero, placing the result in the condition code register. Table 4-4
summarizes the logical operations
Table 4-4. Logic Operations
Instruction Syntax Operand
Operation
Size
AND
(ea), Dn 8,16,32
Source. Destination => Destination
Dn, (ea)
8,16,32
ANDI
#(data), (ea) 8,16,32 Data. Destination
=>
Destination
EaR
Dn, (ea)
8,16,32
Source EEl Destination => Destination
EaRl
#(data), (ea)
8,16,32
Data EEl Destination
=>
Destination
NOT
(ea)
8,16,32
Destination
=>
Destination
OR
(ea), Dn
8,16,32
Source
+
Destination => Destination
Dn, (ea)
8,16,32
ORI
#(data), (ea)
8,16,32 Data
+
Destination
=>
Destination
TST
(ea)
8,16,32
Solurce - 0, to set condition codes
4.3.5 Shift and Rotate Instructions
The arithmetic shift instructions, ASR and ASL, and logical shift instructions,
LSR and LSL, provide shift operations in both directions. The ROR, ROL,
ROXR, and ROXL instructions perform rotate (circular shift) operations, with and
without the extend bit. All shift and rotate operations can be performed on either
registers or memory.
Register shift and rotate operations shift all operand sizes. The shift count may
be specified in the instruction operation word (to shift from 1 to 8 places) or in a
register (modulo 64 shift count).
Memory shift and rotate operations shift word-length operands one bit position
only. The SWAP instruction exchanges the 16-bit halves of a register.
Performance of shift/rotate instructions is enhanced so that use of the ROR and
ROL instructions with a shift count of eight allows fast byte swapping. Table 4-5
is a summary of the shift and rotate operations.
CPU32 REFERENCE MANUAL INSTRUCTION SET
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