Data Types; Organization In Registers; Data Registers - Motorola CPU32 Reference Manual

The vector base register (VBR) contains the base address of the exception
vector table in memory. The displacement of an exception vector is added to
the value in this register to access the vector table.
Alternate function code registers SFC and DFC contain 3-bit function codes.
The CPU32 generates a function code each time it accesses an address.
Specific codes are assigned to each type of access. The codes can be used to
select eight dedicated 4G-byte address spaces. The MOVE instructions can
use registers SFC and DFC to specify the function code of a memory address.
2.3 Data Types
Six basic data types are supported:
1. Bits
2. Binary-Coded Decimal (BCD) Digits
3. Byte Integers (8 bits)
4. Word Integers (16 bits)
5. Long-Word Integers (32 bits)
6. Quad-Word Integers (64 bits)
2.3.1 Organization in Registers
The eight data registers can store data operands of 1, 8, 16,32, and 64 bits and
addresses of 16 or 32 bits. The seven address registers and the two stack
pointers are used for address operands of 16 or 32 bits. The PC is 32 bits wide.
2.3.1.1 Data Registers
Each data register is 32 bits wide. Byte operands occupy the low-order 8 bits,
word operands, the low-order 16 bits, and long-word operands, the entire 32
bits. When a data register is used as either a source or destination operand,
only the appropriate low-order byte or word (in byte or word operations,
respectively) is used or changed- the remaining high-order portion is neither
used nor changed. The least significant bit (LSB) of a long-word integer is
addressed as bit zero, and the most significant bit (MSB) is addressed as bit 31.
Figure 2-4 shows the organization of various types of data in the data registers.
MOTOROLA
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ARCHITECTURE SUMMARY CPU32 REFERENCE MANUAL