Table of Contents
Advertisement
III
ORI
to SR
Operation:
Assembler
Syntax:
Attributes:
Inclusive OR Immediate to Status Register
(Privileged Instruction)
If supervisor state
then Source
+
SR
=>
SR
else TRAP
ORI #(data), SR
Size
=
(Word)
ORI
to SR
Description:
Performs an inclusive OR operation of the immediate operand and the contents of the
status register and stores the result in the status register. All implemented bits of the status
register are affected.
Condition Codes:
x
N
z
v
c
X Set if bit 4 of immediate operand is zero. Unchanged otherwise.
N Set if bit 3 of immediate operand is zero. Unchanged otherwise.
Z Set if bit 2 of immediate operand is zero. Unchanged otherwise.
V
Set if bit
1
of immediate operand is zero. Unchanged otherwise.
C Set if bit
a
of immediate operand is zero. Unchanged otherwise.
Instruction Format:
15
14
13
12
11
10
9
8
7
6
5
o
o
I
0
o
I
0
I
0
I
0
I
o
0
1
I
1
WORD DATA
4
3
2
o
o
I
MOTOROLA
4-132
INSTRUCTION SET
CPU32 REFERENCE MANUAL
Advertisement
Table of Contents
