Motorola CPU32 Reference Manual page 89

III
ANDI
to SR
Operation:
Assembler
Syntax:
Attributes:
AND Immediate to the Status Register
(Privileged Instruction)
If supervisor state
then Source. SR
~SR
else TRAP
ANDI #(data), SR
Size
=
(Word)
ANDI
to SR
Description: Performs an AND operation of the immediate operand with the contents of the status
register and stores the result in the status register. All implemented bits of the status register are
affected.
Condition Codes:
x
N
z
v c
X Cleared if bit 4 of immediate operand is zero. Unchanged otherwise.
N Cleared if bit 3 of immediate operand is zero. Unchanged otherwise.
Z Cleared if bit 2 of immediate operand is zero. Unchanged otherwise.
V Cleared if bit 1 of immediate operand is zero. Unchanged otherwise.
C Cleared if bit 0 of immediate operand is zero. Unchanged otherwise.
Instruction Format:
15 14 13 12 11 10 9 8 7
6 5
4
o
I
0
o
I
0
I
0
I
0
o
0
WORD DATA
3 2
o
o
I
0
MOTOROLA
4-36
INSTRUCTION SET CPU32 REFERENCE MANUAL