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8.3.9 Shift/Rotate Instructions
The shift/rotate instruction table indicates the number of clock periods needed
for the processor to perform the specified operation on the given addressing
mode. Footnotes indicate when to account for the appropriate effective address
times. The number of bits shifted does not affect the execution time, unless
noted. The total number of clock cycles is outside the parentheses. The
numbers inside parentheses (r/p/w) are included in the total clock cycle number.
All timing data assumes two-clock reads and writes.
Instruction
Head
Tail
Cycles
LSd
Dn,Dm
-2
0
(0/1/0)
LSd
#,Dm
4
0
6(0/1/0)
LSd
(FEA)
0
2
6(0/1/1 )
ASd
Dn,Dm
-2
0
(0/1/0)
ASd
#,Dm
4
0
6(0/1/0)
ASd
(FEA)
0
2
6(0/1/1 )
ROd
Dn,Dm
-2
0
(0/1/0)
ROd
#,Dm
4
0
6(0/1/0)
ROd
(FEA)
0
2
6(0/1/1)
ROXd
Dn,Dm
-2
0
(0/1/0)
ROXd
#,Dm
-2
0
(0/1/0)
ROXd
(FEA)
0
2
6(0/1/1 )
NOTES:
1. Head and cycle times can be calculated as follows:
Max (3 + (n/4) + mod(n,4) + mod «(n/4) + mod (n,4) + 1,2), 6)
or derived from the following table.
2. Head and cycle times are calculated as follows: (count
~
63): max (3 + n+ mod (n + 1,2), 6).
3. Head and cycle times are calculated as follows: (count
~
8): max (2 + n+ mod (n,2), 6).
d
=
Direction (left or right)
Clocks
Shift Counts
6
0
1
2
3
4
5
6
8
8
7
10
11
13
14
16
17
20
10
15
18
19
21
22
24
25
28
12
23
26
27
29
30
32
33
36
14
31
34
35
37
38
40
41
44
16
39
42
43
45
46
48
49
52
18
47
50
51
53
54
56
57
60
20
55
58
59
61
62
22
63
9
Note
1
-
-
1
-
-
1
-
-
2
3
-
12
CPU32 REFERENCE MANUAL
INSTRUCTION EXECUTION
TIMING
MOTOROLA
8-23
IE
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