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The SSW for faults in this category contains the following bit pattern:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
I
0
I
0
I
0
I
0
I
81
I
80
I
0
I
AM
I
IN
I
FYI
I
LG
I
SIZ
FUNC
The trace pending bit is always cleared, since the instruction will be restarted
upon return from the handler. Saving a pending exception on the stack would
result in a trace exception being taken prior to restarting the instruction. If the
exception handler does not alter the stacked SR trace bits, the trace is
requeued when the instruction is started.
The breakpoint pending bits are stacked in the SSW, even though the
instruction is restarted upon return from the handler. This avoids problems with
bus state analyzer equipment that has been programmed to breakpoint only the
first access to a specific location, or to count accesses to that location. If this
response is not desired, the exception handler can clear the bits before return.
The RM, IN, RW. LG. FUNC, and SIZ fields all reflect the type of bus cycle that
caused the fault. If the bus cycle was an RMW, the RM bit will be set and the RW
bit will show whether the fault was on a read or write.
6.3.1.3 Type III: Faults During MOVEM Operand Transfer
Bus faults that occur as a result of MOVEM operand transfer are classified as
type III faults. MOVEM Instruction prefetch faults are type II faults.
Type III faults cause an immediate exception that aborts the current instruction.
None of the registers altered during execution of the faulted instruction are
restored prior to execution of the fault handler. This includes any register
predecremented as a result of the effective address calculation or any register
overwritten during instruction execution. Since postincremented registers are
not updated until the end of an instruction, the register retains its preinstruction
value unless overwritten by operand movement.
The SSW for faults in this category contains the following bit pattern:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
I
0
I
1
I
0
I
1R
I
81
I
80
I
ffi
I
0
I
IN
I
FYI
I
LG
I
SIZ
FUNC
MV is set, indicating that MOVEM should be continued from the point where the
fault occurred upon return from the exception handler. TR, B1, and BO are set if
a corresponding exception is pending when the BERR exception is taken. IN is
set if a bus fault occurs while refetching an opcode or an extension word during
instruction restart. RW, LG, SIZ, and FUNC all reflect the type of bus cycle that
CPU32 REFERENCE MANUAL
EXCEPTION
PROCESSING
MOTOROLA
6-21
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