Motorola CPU32 Reference Manual page 92

M68300 series central processor unit
Hide thumbs Also See for CPU32:
Table of Contents

Advertisement

ASL, ASR
Arithmetic Shift
ASL, ASR
Instruction Format (Memory Shifts):
15
14
13
12
11
10
9
8
7
6
5
4
3
2
o
EFFECTIVE ADDRESS
1
1
1
0
0
0
0
dr
1
1
MODE
I
REGISTER
Instruction Fields (Memory Shifts):
dr field -
Specifies the direction of the shift:
o -
Shift right
1 -
Shift left
Effective Address field -
Specifies the operand to be shifted.
Only memory alterable addressing modes are allowed as shown:
Addressing Mode
Mode
Register
Addressing Mode
On
-
-
(xxx).w
An
-
-
(xxx).L
(An)
010
Reg. number: An
#(data)
(An)
+
011
Reg. number: An
-(An)
100
Reg. number: An
(d16, An)
101
Reg. number: An
(d16, PC)
(dS, An, Xn)
110
Reg. number: An
(dS, PC, Xn)
(bd, An, Xn)
110
Reg. number: An
(bd, PC, Xn)
CPU32 REFERENCE MANUAL
INSTRUCTION SET
Mode
111
111
-
-
-
-
Register
000
001
-
-
-
-
MOTOROLA
4-39
III

Advertisement

Table of Contents
loading

Table of Contents