Motorola CPU32 Reference Manual page 60

Table 4-1. Condition Code Computations (Continued)
Operations
x
N
SUBX * *
CMP, CMPI, CMPM
*
DIVS, DIVU *
MULS, MULU
*
SBCD, NBCD
*
U
NEG
* *
NEGX
* *
ASL *
ASL (r =0) *
LSL, ROXL
* *
LSR (r= 0)
ROXL(r= 0) *
ROL
ROL (r=O) *
ASR, LSR, ROXR
* *
ASR, LSR (r = 0)
*
ROXR (r=O)
*
ROR
*
ROR(r=O)
*
z
v
? ?
*
?
*
?
*
?
? U
*
?
? ?
* ?
*
o
*
o
*
o
*
o
*
o
*
o
*
o
*
o
*
o
*
o
*
o
c
Special Definition
V=Sm.Dm.Am+Sm.Om.Rm
? C = Sm • Dm + Rm • Dm
+
Sm • Rm
Z=Z.Rm •...• RO
?
o
o
?
?
v
= Sm • Dm • Am + Sm • Dm • Rm
C = Sm • Dm + Rm • Dm
+
Sm • Rm
v
= Division Overflow
v
= Multiplication Overflow
C = Decimal Borrow
Z=Z.Rm •...• RO
V=Dm.Rm
C=Dm+Rm
V=Dm.Am
? C=Dm+Rm
V= Dm. (Dm-1 + ...
+
Dm - r)+Dm.
? (Dm-1 + ... + Dm - r)
C
=
Dm -
r +
1
o
? C=Dm-r+ 1
o
o
? C= Dr-1
o
? C=Dr-1
o
Note: The followmg notation applies to this table only.
Not affected
U Undefined
?
See special definition
*
General case
X=C
N=Rm
Z=Rm •...• RO
CPU32 REFERENCE MANUAL INSTRUCTION SET
Sm Source operand MSB
Om
Destination operand MSB
Rm Result operand MSS
R Register tested
r Shift count
LB Lower bou nd
US Upper bound
MOTOROLA
4-7
III