Reference Design Files; Installation Is Complete - Xilinx Virtex-6 FPGA Getting Started Manual

Reference Design Files

The design checklist in
for the reference designs. After registration, reference design files are available for
download at ug664.zip.
Table 2: Design Checklist
General
Developer Name
Target devices (stepping level, ES, production, speed grades)
Source code provided
Source code format
Design uses code or IP from an existing reference design or
application note, third party, CORE Generator software
Simulation
Functional simulation performed
Timing simulation performed
Testbench used for functional and timing simulations
Testbench format
Simulator software/version used
SPICE/IBIS simulations
Implementation
Synthesis software tools/version used
Implementation software tools/versions used
Static timing analysis performed
Hardware Verification
Hardware verified
Hardware platform used for verification

Installation is Complete

The Xilinx design tools have been successfully installed, the CORE Generator tool flow for
IP delivery is better understood, and the FPGA application is ready to be designed and
implemented targeting the Virtex-6 LXT architecture.
For updated information on this Virtex-6 FPGA Connectivity Kit, go to
http://www.xilinx.com/v6connkit. Check this page regularly for the latest in
documentation, FAQs, reference design examples, product updates, and known issues.
Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Table 2
Parameter
www.xilinx.com
includes simulation, implementation, and hardware details
XC6VLX240T-1-FF1156
Y (for custom logic only)
Uses code from a third party and LogiCORE IP from
the CORE Generator software
Y (for functional simulations)
System Verilog (inhouse verification), Verilog
(customer deliverable)
ModelSim Questa 6.5a (inhouse verification)/
ModelSim 6.4b (out-of-box simulation support)
ML605 board and FMC X104 Connectivity daughter
Reference Design Files
Description
Xilinx
Verilog
Y
N
N
XST
ISE Design Suite
Y
Y
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