Next Steps; Connectivity Trd Modules - Xilinx Virtex-6 FPGA Getting Started Manual

Next Steps

Connectivity TRD Modules

This section outlines the correlation between the design modules and corresponding
design source files for the various blocks of the design. Refer to
detailed block diagram of the Virtex-6 FPGA Connectivity TRD.
file organization per module.
Table 1: Design File Organization for the Virtex-6 FPGA Connectivity TRD
Module Name
Top-Level Module:
Virtex-6 FPGA
Connectivity TRD
PCI Express (x4)
Packet DMA
Multiport Virtual FIFO
Memory Controller Block
XAUI
Clocking, Reset, Register
Interface
Software Device Driver
Software Application/GUI
For functional details on these modules, refer to the "Functional Description" chapter in
UG379, Virtex-6 FPGA Connectivity Targeted Reference Design with AXI4 Protocol User Guide.
Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Source Files/Directories
v6_pcie_10Gdma_ddr3_
xaui_axi
pcie
dma
virtual_fifo
mig
xaui
reset_control,
registers
linux_driver,
windows_driver
linux_driver/xpmon,
windows_driver/xpmon
www.xilinx.com
LogiCORE IP
✓
(Endpoint for PCI Express
core with AXI4-Stream
interface - CORE generator
output)
OR
(Endpoint for PCI Express
core with transaction
interface - CORE generator
output)
✓
(MIG - CORE Generator
output)
✓
(XAUI core -
CORE Generator output)
Next Steps
Figure 1, page 11 for the
Table 1 shows the design
Connectivity TRD
Source
✓
Netlist deliverable only
(from Northwest Logic)
✓
✓
✓
✓
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