Revision History - Xilinx Virtex-6 FPGA Getting Started Manual

Connectivity kit
Hide thumbs Also See for Virtex-6 FPGA:
Table of Contents

Advertisement

Notice of Disclaimer
The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum
extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising
under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or
consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action
brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product
specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are
subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be
subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be
fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical
Applications: http://www.xilinx.com/warranty.htm#critapps.
© Copyright 2010–2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included
herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used
under license. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.
Date
Version
02/26/10
1.0
06/11/10
1.1
08/10/10
1.2
10/05/10
1.3
07/06/11
1.4
Virtex-6 FPGA Connectivity Kit Getting Started
Initial Xilinx release.
Removed references to specific release numbers for the ISE Design Suite, where
applicable. Replaced
Figure
Figure
27.
Removed update DVD from
step b, page
31. Removed DDR3 from Raw Data Path bullet in
step
2b on
page
33, changed the minimum value of the range from 128 to 64 for the XAUI
and Raw Data paths and changed the Raw Data path option to one Packet Size instead
of a minimum and a maximum. In
Added the note under
Figure
"ISE 11.4 Software Update Installation" sections with a link to the Installation, Licensing,
and Release Notes document. In
number from the path. In
added the note on
page
42. Changed the command in
names of the BIT and MCS files in
Windows based script in
step
shell opening from
step
8d on
In
step
4c on
page
42, changed the filename to mig3_5.xco from mig3_4.xco. In
Table
2, changed the implementation software tool entry to ISE Design Suite.
Added information for AXI4 protocol.
Removed descriptions of Virtex-6 FPGA Connectivity TRD being available in non-AXI4
protocol version throughout. Replaced v6_trd_quickstart with v6_trd_lin_quickstart.
Added Windows platform to
Features. Updated
step
6c on
Figure
21. Added
Install Linux Driver
www.xilinx.com
Revision
1,
Figure
22,
Figure
23,
Figure
Connectivity Kit
Contents. Added "in loopback mode" to
step
2c on
page
35, indicated to click Start test.
26. Replaced the "ISE 11.1 Software Installation" and
step 8, page
40, removed the ISE Design Suite release
Modifying the Virtex-6 FPGA Targeted Reference
step
5d on
page
43. Removed "double-click" from the
8c on
page
44. Removed sentence about the command
page
44. Added the
Next Steps
Board and Connectivity Targeted Reference Design
page
14. Added
Install Windows
heading before
24,
Figure
25,
Figure
26, and
step
2a on
page
33. In
Design,
step
4c on
page
42. Changed the
section.
Driver. Updated
step 12
on
page
27.
UG664 (v1.4) July 6, 2011

Advertisement

Table of Contents
loading

Table of Contents