Test Setup - Xilinx Virtex-6 FPGA Getting Started Manual

Modifying the Virtex-6 FPGA Targeted Reference Design
8.
X-Ref Target - Figure 37
The Virtex-6 FPGA Connectivity TRD is now modified and programmed into the Platform
Flash and will automatically configure at power up.

Test Setup

Follow
insert the board in the PC system and configure the FPGA with the design changes that
were implemented. Software modifications corresponding to hardware modifications are
also required to ensure that the TRD is functioning correctly.
44
Program the onboard Platform Flash:
a. Open a terminal window.
b. Navigate to the v6_pcie_10Gdma_ddr3_xaui_axi/design/implement/
results_x4_gen2_240t directory.
c. Execute the FPGA programming script at the command prompt. This operation
takes approximately 600 to 800 seconds to complete.
- $ impact -batch ml605program.cmd (for Linux based machines)
- $ ml605program.bat (for Windows based machines)
d. After successful completion, the Programmed successfully message should
appear.
Figure 37: Programming Was Successful
e. Turn off the power switch and remove the power connector.
f. Carefully remove the mini USB cable.
step 1 through step 6 in
www.xilinx.com
Hardware Demonstration Setup Instructions, page 12
Virtex-6 FPGA Connectivity Kit Getting Started
UG664_38_011610
to
UG664 (v1.4) July 6, 2011