Multiport Virtual Fifo And Memory Controller Block - Xilinx Virtex-6 FPGA Getting Started Manual

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Multiport Virtual FIFO and Memory Controller Block

Figure 56
block.
X-Ref Target - Figure 56
X-Ref Target - Figure 57
60
shows the design module for the multiport virtual FIFO and memory controller
Figure 57 shows the design file structure.
@250 MHz
64
WR_Data
Control
Control
RD_Data
64
64
WR_Data
Control
Control
RD_Data
64
@250 MHz
Figure 56: Multiport Virtual FIFO and Memory Controller Block Design Module
Figure 57: Multiport Virtual FIFO and Memory Controller Design FIles
www.xilinx.com
@156.25 MHz
64
RD_Data
Control
Control
WR_Data
64
Multiport
Virtual
FIFO
64
RD_Data
Control
Control
WR_Data
64
@250 MHz
Native
256
Interface
of DDR3
@200 MHz
Memory
Controller
256
v6_pcie_10Gdma_ddr3_xaui_axi
design
source
virtual_fifo
ip_cores
mig
UG664_21_090810
Virtex-6 FPGA Connectivity Kit Getting Started
@400 MHz
DDR3
64
UG664_20_060110
UG664 (v1.4) July 6, 2011