Xaui - Xilinx Virtex-6 FPGA Getting Started Manual

XAUI

Figure 58
X-Ref Target - Figure 58
X-Ref Target - Figure 59
Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
shows the XAUI design module.
@156.25 MHz
Figure 58: XAUI Design Module
v6_pcie_10Gdma_ddr3_xaui_axi
design
Figure 59: XAUI Design FIles
www.xilinx.com
Figure 59 shows the design file structure.
Data
Control
Control
Data
64
UG664_22_060110
ip_cores
xaui
UG664_23_090810
Next Steps
61