Packet Dma - Xilinx Virtex-6 FPGA Getting Started Manual

Packet DMA

Figure 54
structure.
X-Ref Target - Figure 54
X-Ref Target - Figure 55
Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
shows the design module for Packet DMA.
Figure 54: Packet DMA Design Module
v6_pcie_10Gdma_ddr3_xaui_axi
Figure 55: Packet DMA Design FIles
www.xilinx.com
Figure 55
@250 MHz
64
S2C_Data
S2C_Ctrl
C2S_Ctrl
C2S_Data
Packet
DMA
64
S2C_Data
S2C_Ctrl
C2S_Ctrl
C2S_Data
@250 MHz
Register
Interface
UG664_18_051911
design
ip_cores
dma
UG664_19_090810
Next Steps
shows the design file
59