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Detailed Example Design
This chapter provides detailed information about the example design, including a
description of files and the directory structure generated by the Xilinx
tool, the purpose and contents of the provided scripts, the contents of the example HDL
wrappers, and the operation of the demonstration test bench.
Directory and File Structure
Spartan-6 FPGA GTP Transceiver Wizard v1.8
UG546 (v1.8) December 14, 2010
<project directory>
topdirectory
Top-level project directory; name is user-defined
<project directory>/<component name>
Core release notes file.
<component name>/doc
Product documentation
<component name>/example design
Verilog and VHDL design files
<component name>/implement
Implementation script files
/implement/results
Results directory, created after implementation scripts are run, and
contains implement script results
<component name>/simulation
Simulation scripts
/simulation/functional
Functional simulation files
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Chapter 5
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CORE Generator™
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