Xilinx LogiCORE IP Spartan-6 Getting Started Manual page 38

Chapter 3: Running the Wizard
Table 3-23: Clock Correction
Option
Use Clock Correction
Sequence Length
Rx Buffer Max Latency
Rx Buffer Min Latency
Use Two Clock
Correction Sequences
38
Enables receiver clock correction logic using unique character sequences. When recognized,
these sequences allow for adding or deleting characters in the receive buffer to prevent buffer
underflow/overflow due to small differences in the transmit/receive clock frequencies.
Select from the drop down list the number of characters (subsequences) in the unique clock
correction sequence.
The PCI EXPRESS example uses 1.
Select from the drop down list the maximum number of characters to permit in the receive
buffer before clock correction attempts to delete incoming clock correction sequences. Also
determines the maximum latency of the receive buffer in RXUSRCLK cycles.
The PCI EXPRESS example uses 20.
Select from the drop down list the minimum number of characters to permit in the receive
buffer before clock correction attempts to add extra clock correction sequences to the receive
buffer. Also determines the minimum latency of the receive buffer in RXUSRCLK cycles.
The PCI EXPRESS example uses 28.
Activates the optional second Clock Correction sequence. Detection of either sequence
triggers clock correction.
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Description
Spartan-6 FPGA GTP Transceiver Wizard v1.8
UG546 (v1.8) December 14, 2010