Example Design - Xilinx LogiCORE IP Spartan-6 Getting Started Manual

Chapter 5: Detailed Example Design

Example Design

The example design that is delivered with the wrappers helps core designers understand
how to use the wrappers and GTP transceivers in a design. The example design is shown
in
X-Ref Target - Figure 5-1
The example design connects a frame generator and a frame checker to the wrapper. The
frame generator transmits an incrementing counting pattern while the frame checker
monitors the received data for correctness. The frame generator counting pattern is stored
in block RAM. This pattern can be easily modified by altering the parameters in the frame
generator instantiation. The frame checker contains the same pattern in block RAM and
compares it with the received data. An error counter in the frame checker keeps a track of
how many errors have occurred.
If comma alignment is enabled, the comma character will be placed within the counting
pattern. Similarly, if channel bonding is enabled, the channel bonding sequence would be
interspersed within the counting pattern. The frame check works by first scanning the
received data for the START_OF_PACKET_CHAR. In 8B/10B designs, this is the comma
alignment character. Once the START_OF_PACKET_CHAR has been found, the received
data will continuously be compared to the counting pattern stored in the block RAM at
each RXUSRCLK2 cycle. Once comparison has begun, if the received data ever fails to
match the data in the block RAM, checking of receive data will immediately stop, an error
counter will be incremented and the frame checker will return to searching for the
START_OF_PACKET_CHAR.
For 64B/66B and 64B/67B example designs, the frame generator has scrambler logic while
the frame checker has descrambler and block synchronization logic.
If the TX buffer is bypassed, the TX_SYNC module is instantiated in the example design
and connected to the wrapper. The module performs the TX phase alignment procedure
outlined in the Spartan-6 FPGA GTP Transceivers User Guide. Similarly, if the RX buffer is
bypassed, the RX_SYNC module is instantiated in the example design and connected to
50
Figure 5-1.
Test Bench
FRAME_GEN
FRAME_CHECK
Figure 5-1: Wrapper Block Diagram
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Example Design
Wrapper
GTP
Transceiver
Ports
GTPA1_DUAL
Transceiver
Tile(s)
Configuration
Parameters
Spartan-6 FPGA GTP Transceiver Wizard v1.8
UG546 (v1.8) December 14, 2010
GSG546_05_01_071509