Related Manuals for Xilinx LogiCORE IP Spartan-6
Summary of Contents for Xilinx LogiCORE IP Spartan-6
- Page 1 ® LogiCORE™ IP Spartan FPGA GTP Transceiver Wizard v1.8 Getting Started Guide UG546 (v1.8) December 14, 2010...
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Page 2: Revision History
Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information. -
Page 3: Table Of Contents
......... . . 10 Related Xilinx Documents . - Page 4 ..........51 www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8...
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Page 5: Preface: About This Guide
Xilinx CORE Generator tool, the purpose and contents of the provided scripts, the contents of the example HDL wrappers, and the operation of the demonstration test bench. -
Page 6: Typographical
The prefix ‘0x’ or the suffix ‘h’ A read of address 0x00112975 indicate hexadecimal notation returned 45524943h. Notations An ‘_n’ means the signal is usr_teof_n is active low. active low www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010... -
Page 7: Online Document
Refer to “Title Formats” in Chapter 1 for details. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010... - Page 8 Preface: About This Guide www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010...
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Page 9: Chapter 1: Introduction
Parameters GSG546_01_01_070709 Figure 1-1: GTP Transceiver Wizard Wrapper About the Wizard The Spartan-6 FPGA GTP Transceiver Wizard is a Xilinx CORE Generator tool, available at ® the Xilinx IP Center. For information about system requirements, installation, and licensing options, see Chapter 2, Installation and Licensing. -
Page 10: Recommended Design Experience
For technical support, go to www.xilinx.com/support. Questions are routed to a team of engineers with expertise using the Spartan-6 FPGA GTP Transceiver Wizard. Xilinx provides technical support for use of this product as described in the LogiCORE IP Spartan-6 FPGA GTP Transceiver Wizard v1.8 Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines. -
Page 11: Document
(you believe something could be improved) or reporting a defect (you believe something isn’t working correctly). Document For comments or suggestions about this document, please submit a WebCase from www.xilinx.com/support. (Registration is required to log in to WebCase.) Be sure to include the following information: • Document title •... - Page 12 Chapter 1: Introduction www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010...
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Page 13: System Requirements
Installing the Wizard, otherwise do the following: Click Login at the top of the Xilinx home page then follow the onscreen instructions to create a MySupport account. Install the ISE 12.4 software. For the software installation instructions, see the ISE Design Suite Release Notes and Installation Guide available in ISE software Documentation. -
Page 14: Installing The Wizard
Determine if the installation was successful by verifying that Spartan-6 FPGA GTP Transceiver Wizard 1.8 appears at the following location in the Functional Categories list: /FPGA Features and Design/IO Interfaces www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010... -
Page 15: Chapter 3: Running The Wizard
PCI EXPRESS example design. X-Ref Target - Figure 3-1 Example Design PCIE Wrapper Transceiver Ports Test Bench GTPA1_DUAL Tile(s) PCIE Config Parameters GSG546_03_01_021509 Figure 3-1: Example Design Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010... -
Page 16: Setting Up The Project
Choose File → New Project (Figure 3-2). Optionally change the name of the .cgp file Click Save. X-Ref Target - Figure 3-2 Figure 3-2: Starting a New Project www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010... -
Page 17: Setting The Project Options
Click Generation in the option tree and select either Verilog or VHDL as the output language. Click OK. X-Ref Target - Figure 3-3 Figure 3-3: Target Architecture Setting Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010... -
Page 18: Generating The Core
/FPGA Features & Design/IO Interfaces. (See Figure 3-4) Double-click Spartan-6 FPGA GTP Transceiver Wizard 1.8 to launch the Wizard. X-Ref Target - Figure 3-4 Figure 3-4: Locating the GTP Transceiver Wizard www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010... -
Page 19: Gtp Placement And Clocking
(two GTPA1_DUAL primitives). Table 3-1 describes the GTP transceiver selection and Reference Clock options. X-Ref Target - Figure 3-5 Figure 3-5: GTP Placement and Clocking - Page 1 Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010... - Page 20 Not available on devices with fewer than four transceiver pairs. External GTPA1_DUAL reference clock signal local to second lower REFCLK_X1Y1 transceiver pair. Not available on devices with fewer than four transceiver pairs. www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010...
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Page 21: Line Rate And Protocol Template
GTP1. The PCI EXPRESS example uses the pcie protocol template. Because both transceivers are configured identically, the protocol template option for GTP1 is set to Use GTP0 settings. Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010... - Page 22 8-bit bytes (32 bits). If 8B/10B encoding is not selected, the transmitter application interface data path width will be set to four 10-bit bytes (40 bits). www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010...
- Page 23 8-bit bytes (32 bits). If 8B/10B encoding is not selected, the receiver application interface data path width will be set to four 10-bit bytes (40 bits). Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010...
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Page 24: 10B Optional Ports
Two-bit wide port indicates current running disparity of the 8B/10B decoder on a per- RXRUNDISP byte basis. High-order bit corresponds to high-order byte of data path. www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010... -
Page 25: Synchronization And Clocking
RX buffer is deselected, then the RX Phase Alignment circuit is enabled. The PCI EXPRESS example does not use the RX Phase Alignment circuit. X-Ref Target - Figure 3-8 Figure 3-8: Synchronization and Clocking - Page 4 Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010... - Page 26 RXBUFSTATUS Alignment circuit is used. Active-High reset signal for the RX elastic buffer logic. This option is not available when the RXBUFRESET RX Phase Alignment circuit is used. www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010...
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Page 27: Rx Comma Alignment
RX comma detection and alignment logic. The settings are detailed in Table 3-10, page X-Ref Target - Figure 3-9 Figure 3-9: RX Comma Alignment - Page 5 Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010... - Page 28 Active-High signal indicating that byte alignment has changed with a recent comma detection. RXBYTEREALIGN Note that data errors can occur with this condition. Active-High signal indicating the comma alignment logic has detected a comma pattern in the RXCOMMADET data stream. www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010...
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Page 29: Preemphasis, Termination, And Equalization
The PCI EXPRESS example uses the default setting 1001 (1110 mV). See the Spartan-6 FPGA GTP Transceivers User Guide for a table mapping TXDIFFCTRL value settings to differential swing levels. Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010... - Page 30 Active-High reset signal causes the CDR logic to unlock and return to the shared PLL RXCDRRESET frequency. RXPOLARITY Active-High signal inverts the polarity of the receive data signal. www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010...
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Page 31: Rx Oob, Prbs, And Loss Of Sync
OOB signal. This option is not available if the Use RX OOB Detection Threshold OOB signal detection option is not selected. See the Spartan-6 FPGA GTP Transceivers User Guide for more information about the OOB Detection Threshold levels. Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010... - Page 32 Integer value between 1 and 128 representing the number of consecutive valid characters needed to cancel out the appearance of one invalid Good Bytes to Reduce Error Count by 1 character. The PCI EXPRESS example uses 8. www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010...
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Page 33: Rx Pci Express, Sata Features
PCI EXPRESS and Serial ATA (SATA) features. X-Ref Target - Figure 3-12 Figure 3-12: RX PCI Express, SATA Features - Page 8 Table 3-19, page 34 details the receiver SATA configuration options. Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010... - Page 34 COMINIT/COMRESET or COMWAKE. This value defaults to 3 per the SATA Idles specification. This option is not available if RXSTATUS encoding format is set to PCI EXPRESS. Table 3-20, page 35 details the receiver PCI Express configuration options. www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010...
- Page 35 EXPRESS mode this option is used for electrical idle modes. Function depends TXELECIDLE on the state of TXPOWERDOWN, RXPOWERDOWN, TXELECIDLE, TXCHARDISPMODE, and TXCHARDISPVAL. Active-High, PCI EXPRESS receive detect support signal. Indicates completion PHYSTATUS of several PHY functions. Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010...
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Page 36: Channel Bonding, Clock Correction
The protocol template option for GTP1 (Wizard Page 2) must be set to Use GTP0 settings to enable the Channel Bonding settings. Table 3-21, page 37 describes the common Channel Bonding settings. www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010... - Page 37 Multiple-byte sequences can have wild card symbols by checking this option. Unused bytes in the Don’t Care sequence automatically have this option set. Table 3-23, page 38 describes the Clock Correction settings. Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010...
- Page 38 Also determines the minimum latency of the receive buffer in RXUSRCLK cycles. The PCI EXPRESS example uses 28. Use Two Clock Activates the optional second Clock Correction sequence. Detection of either sequence Correction Sequences triggers clock correction. www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010...
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Page 39: Clock Correction Sequence
Multiple-byte sequences can have wild card symbols by checking this option. Unused bytes in the Don’t Care sequence automatically have this option set. Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010... -
Page 40: Summary
3-15) provides a summary of the selected configuration parameters. After reviewing the settings, click Generate to exit and generate the wrapper. X-Ref Target - Figure 3-15 Figure 3-15: Summary - Page 11 www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010... -
Page 41: Chapter 4: Quick Start Example Design
The generated output also includes several scripts to assist in running the Xilinx software. From the command prompt, navigate to the project directory and type the following: For Windows >... -
Page 42: Functional Simulation Of The Example Design
® ® 12.4, available in the ISE Software Documentation for instructions on how to compile ISE simulation libraries. Table 4-1: Required ModelSim Simulation Libraries Library Source Directories < Xilinx dir >/spartan6/verilog/src/unisims Verilog UNISIMS_VER < Xilinx dir >/spartan6/secureip/mti Xilinx dir <... -
Page 43: Using The Ise Simulator
Using ChipScope Pro Cores with the Spartan-6 FPGA GTP Transceiver Wizard Core Using the ISE Simulator When using the ISE Simulator (ISim), the required Xilinx simulation device libraries are precompiled, and are updated automatically when service packs and IP updates are installed. - Page 44 Chapter 4: Quick Start Example Design www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010...
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Page 45: Chapter 5: Detailed Example Design
This chapter provides detailed information about the example design, including a ® description of files and the directory structure generated by the Xilinx CORE Generator™ tool, the purpose and contents of the provided scripts, the contents of the example HDL wrappers, and the operation of the demonstration test bench. -
Page 46: Directory And File Contents
Table 5-2: GTP Wrapper Component Name Name Description <project_dir>/<component_name> Release notes for the GTP Wizard. s6_gtpwizard_readme.txt Protocol description for the selected protocol <component_name>.pf from the GTP Wizard. Back to Top www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010... -
Page 47: Component Name>/Doc
Name Description <project_dir>/<component_name>/doc Spartan-6 FPGA GTP Transceiver Wizard v1.8 Data Sheet s6_gtpwizard_ds713.pdf LogiCORE IP Spartan-6 FPGA GTP Transceiver Wizard s6_gtpwizard_gsg546.pdf v1.8 Getting Started Guide Back to Top <component name>/example design The example design directory contains the example design files provided with the core. -
Page 48: Component Name>/Implement
Xilinx tool flow. A Windows batch file that processes the example implement_synplify.bat design through Synplify synthesis and the Xilinx tool flow. A Linux shell script that processes the example design implement_synplify.sh through Synplify synthesis and the Xilinx tool flow. -
Page 49: Component Name>/Simulation
Script for adding GTP Wrapper signals to the ModelSim wave_mti.do wave viewer. Script for adding GTP Wrapper signals to the Cadence IUS wave_ncsim.sv wave viewer. Back to Top Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010... -
Page 50: Example Design
Spartan-6 FPGA GTP Transceivers User Guide. Similarly, if the RX buffer is bypassed, the RX_SYNC module is instantiated in the example design and connected to www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8 UG546 (v1.8) December 14, 2010... -
Page 51: Example Design Hierarchy
GUI. Example Design Hierarchy The hierarchy for the design used in this example is as follows: example_tb |___example_mgt_top |___mgt_userclk_source_pll |___ibufds |___frame_gen |___frame_check |___pcie_wrapper |___pcie_wrapper_tile |___gtpa1_dual Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com UG546 (v1.8) December 14, 2010...