Xilinx LogiCORE IP Spartan-6 Getting Started Manual page 26

Chapter 3: Running the Wizard
Table 3-7
Table 3-7: TXUSRCLK and RXUSRCLK Source
Option
TXUSRCLK is driven by TXOUTCLK. This option is not available if the TX Phase Alignment
TXOUTCLK
Circuit is used.
TXUSRCLK is driven by REFCLKOUT. This option is required if the TX Phase Alignment
REFCLKOUT
Circuit is used.
TX
Brings the TXUSRCLK input signal out to a port at the top-level of the wrapper so it can be
Enable External provided by the application. Optionally available when single-byte data path width is used
TXUSRCLK and TX Buffer Bypass is disabled. Not available for two-byte data path width. Mandatory with
4-byte data path width.
RXUSRCLK is driven by TXOUTCLK. This option is not available if the RX Phase Alignment
TXOUTCLK
Circuit is used.
RXUSRCLK is driven by RXRECCLK. This option is required if the RX Phase Alignment
RXRECCLK
Circuit is used.
RXUSRCLK is driven by REFCLKOUT. This option is not available if the RX Phase Alignment
RX
REFCLKOUT
Circuit is used.
Brings the RXUSRCLK input signal out to a port at the top-level of the wrapper so it can be
Enable External provided by the application. Optionally available when single-byte data path width is used
RXUSRCLK without channel bonding. Not available for two-byte data path width. Mandatory with 4-byte
data path width.
Table 3-8
receiver CDR logic for the desired PPM tolerance range.
Table 3-8: PPM Offset
Option
0 (Synchronous) Use with synchronous applications (zero tolerance).
Up to ± 100 For applications where clock tolerance is below 100 PPM.
Up to ± 500 For applications where clock tolerance is below 500 PPM.
Table 3-9
Table 3-9: Optional Ports
Option
RXRESET Active-High reset signal for the receiver PCS logic.
Recovered clock signal from the CDR logic. This option is required when selected as an input
RXRECCLK
to RXUSRCLK.
Indicates the condition of the RX elastic buffer. This option is not available when the RX Phase
RXBUFSTATUS
Alignment circuit is used.
Active-High reset signal for the RX elastic buffer logic. This option is not available when the
RXBUFRESET
RX Phase Alignment circuit is used.
26
details the TXUSRCLK and RXUSRCLK source signal options.
shows the available PPM Offset settings. The PPM Offset setting optimizes the
shows the optional ports available for synchronization and clocking.
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Description
Description
Description
Spartan-6 FPGA GTP Transceiver Wizard v1.8
UG546 (v1.8) December 14, 2010