Xilinx LogiCORE IP Spartan-6 Getting Started Manual page 23

Table 3-5
Table 3-5: RX Settings
Option
Line Rate
None
Decoding None (MSB First)
8B/10B
8
10
16
Data Path Width
20
32
40
Spartan-6 FPGA GTP Transceiver Wizard v1.8
UG546 (v1.8) December 14, 2010
details the RX Settings options.
Set to the desired target line rate in Gbps. Can be independent of the transmit
line rate. The line rate has option of selecting No_RX. This option disables all
the RX ports in the wrapper when selected.
The PCI EXPRESS example uses 2.5 Gbps.
Data stream is passed with no conversion.
Same as above but reorders bytes for applications expecting most significant
byte first.
Data stream is passed to an internal 8B/10B encoder prior to transmission.
Sets both the internal receiver data path and the receiver application interface
data path width to a single 8-bit byte.
Sets the internal receiver data path width to a single 10-bit byte. If 8B/10B
encoding is selected, the receiver application interface data path width will be
set to 8 bits.
Sets the internal receiver data path width to a single 8-bit byte. Sets the
receiver application interface data path width to two 8-bit bytes (16 bits).
Sets the internal receiver data path width to a single 10-bit byte. If 8B/10B
encoding is selected, the receiver application interface data path width will be
set to two 8-bit bytes (16 bits). If 8B/10B encoding is not selected, the receiver
application interface data path width will be set to two 10-bit bytes (20 bits).
Sets the internal receiver data path width to a single 8-bit byte. Sets the
receiver application interface data path width to four 8-bit bytes (32 bits).
Sets the internal receiver data path width to a single 10-bit byte. If 8B/10B
encoding is selected, the receiver application interface data path width will be
set to four 8-bit bytes (32 bits). If 8B/10B encoding is not selected, the receiver
application interface data path width will be set to four 10-bit bytes (40 bits).
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Generating the Core
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