Functional Simulation Of The Example Design; Using Modelsim - Xilinx LogiCORE IP Spartan-6 Getting Started Manual

Chapter 4: Quick Start Example Design

Functional Simulation of the Example Design

Using ModelSim

The Spartan-6 FPGA GTP Transceiver Wizard provides a quick way to simulate and
observe the behavior of the wrapper using the provided example design and script files.
Prior to simulating the wrapper with ModelSim, the functional (gate-level) simulation
models must be generated. All source files in the following directories must be compiled to
a single library as shown in
ISE
compile ISE simulation libraries.
Table 4-1: Required ModelSim Simulation Libraries
HDL Library
Verilog UNISIMS_VER
VHDL UNISIM
The Wizard provides a command line script for use within ModelSim. To run a VHDL or
Verilog ModelSim simulation of the wrapper, use the following instructions:
1.
2.
3.
The ModelSim script compiles the example design and test bench, and adds the relevant
signals to the wave window.
42
Table
®
12.4, available in the ISE
< Xilinx dir
< Xilinx dir
Xilinx dir
<
Xilinx dir
<
Launch the Modelsim simulator and set the current directory to
<project_directory>/<component_name>/simulation/functional
Set the MTI_LIBS variable:
modelsim> setenv MTI_LIBS <path to compiled libraries>
Launch the simulation script:
modelsim> do simulate_mti.do
www.xilinx.com
4-1. See the Synthesis and Simulation Design Guide for
®
Software Documentation for instructions on how to
Source Directories
>/spartan6/verilog/src/unisims
>/spartan6/secureip/mti
>/spartan6/vhdl/src/unisims/primitive
>/spartan6/secureip/mti
Spartan-6 FPGA GTP Transceiver Wizard v1.8
UG546 (v1.8) December 14, 2010