Example Design Hierarchy - Xilinx LogiCORE IP Spartan-6 Getting Started Manual

the wrapper. The RX_SYNC module demonstrates the RX phase-alignment procedure
outlined in the Spartan-6 FPGA GTP Transceivers User Guide.
The example design also demonstrates how to properly connect clocks to GTX transceiver
ports TXUSRCLK, TXUSRCLK2, RXUSRCLK and RXUSRCLK2. Properly configured
DCM (Digital Clock manager), PLL (Phase lock loop) wrappers are also provided if they
are required to generate user clocks for the instantiated GTP transceivers.
The example design may be synthesized using XST or Synplify Pro, implemented with
ISE® software and then observed in hardware using the Chipscope Pro tools. RX output
ports such as RXDATA can be observed on the ChipScope Pro ILA core while input ports
can be controlled from the ChipScope Pro VIO core. A ChipScope Pro project file is also
included with each example design.
For the example design to work properly in simulation or in hardware, both the transmit
and receive side need to be configured with the same line rate, encoding and datapath
width in the GUI.

Example Design Hierarchy

The hierarchy for the design used in this example is as follows:
Spartan-6 FPGA GTP Transceiver Wizard v1.8
UG546 (v1.8) December 14, 2010
example_tb
|___example_mgt_top
|___mgt_userclk_source_pll
|___ibufds
|___frame_gen
|___frame_check
|___pcie_wrapper
|___pcie_wrapper_tile
|___gtpa1_dual
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Example Design Hierarchy
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