Xilinx LogiCORE IP Spartan-6 Getting Started Manual page 20

Chapter 3: Running the Wizard
Table 3-1: Select Transceiver and Reference Clocks
Table 3-2: Reference Clock Source Options
20
Option
Select the individual GTPA1_DUAL transceiver pairs by location to be
Tile Location used in the target design. The PCI EXPRESS example requires one
transceiver pair.
Determines the source for the reference clock signal provided to the
GTP0 transceiver in the selected GTPA1_DUAL primitive (see
Table 3-2, page
provided for each GTPA1_DUAL. Individual transceivers have access
GTP0 REFCLK
to the reference clock signals for the two horizontally adjacent
GTPA1_DUAL primitives allowing two primitives to share a single
reference clock signal. The PCI EXPRESS example uses the REFCLK
X0Y0 signal from the upper pair of selected primitives.
GTP1 REFCLK Same as above for the GTP1 transceiver.
Advanced Use this check box to bring out all possible reference clock ports to the
Clocking generated wrapper.
Option
GREFCLK Reference clock driven by internal fabric. Lowest performance option.
External GTPA1_DUAL reference clock signal local to first upper
REFCLK_X0Y0
transceiver pair.
External GTPA1_DUAL reference clock signal local to second upper
REFCLK_X1Y0
transceiver pair.
External GTPA1_DUAL reference clock signal local to first lower
REFCLK_X0Y1 transceiver pair. Not available on devices with fewer than four
transceiver pairs.
External GTPA1_DUAL reference clock signal local to second lower
REFCLK_X1Y1 transceiver pair. Not available on devices with fewer than four
transceiver pairs.
www.xilinx.com
Description
20). Differential clock signal input pin pairs are
Description
Spartan-6 FPGA GTP Transceiver Wizard v1.8
UG546 (v1.8) December 14, 2010