Table of Contents
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Section 5
Overview .................................................................................................................................................5-1
Transmit Function ...................................................................................................................................5-1
Jabber Control Function ..........................................................................................................................5-1
SQE Function ..........................................................................................................................................5-3
Receive Function ....................................................................................................................................5-3
Polarity Reverse Function ..............................................................................................................5-3
Collision Detection Function ...........................................................................................................5-4
Loopback Function ..................................................................................................................................5-5
Link Integrity Test.....................................................................................................................................5-5
Section 6
Overview .................................................................................................................................................6-1
100Mbit/s Transmit Circuits .....................................................................................................................6-2
Frequency Synthesizer ...................................................................................................................6-3
Crystal Oscillator ............................................................................................................................6-3
Transmit Twisted-Pair Driver ..........................................................................................................6-4
100Mbit/s Receive Circuits ......................................................................................................................6-5
Receiver Buffer ...............................................................................................................................6-5
Adaptive Equalizer ..........................................................................................................................6-6
Base Line Restore ..........................................................................................................................6-6
Clock Recovery ..............................................................................................................................6-6
10Mbit/s transmit circuits .........................................................................................................................6-7
Transmit Wave Shaper ...........................................................................................................................6-7
10MBit/s Receive Circuits .......................................................................................................................6-7
Receiver .........................................................................................................................................6-7
Section 7
Overview .................................................................................................................................................7-1
Register Definitions .................................................................................................................................7-2
PHY registers ..........................................................................................................................................7-3
Base Mode Control : register 0 .......................................................................................................7-3
base mode status : register 1 .........................................................................................................7-5
PHY identifier 1 : register 2 .............................................................................................................7-6
PHY identifier 2 : register 3 .............................................................................................................7-6
Auto-negotiation Advertisement : Register 4 ..................................................................................7-7
Auto-negotiation Link Partner Ability : Register 5 ...........................................................................7-8
Auto-negotiation Expansion : Register 6 ........................................................................................7-9
Auto-negotiation Next Page Transmit Register : Register 7 ...........................................................7-10
10Base-T Control Register : Register 16 ........................................................................................7-11
100Base-TX Control Register : Register 17 ...................................................................................7-12
PHY Address Register : Register 18 ..............................................................................................7-12
Map Table Register 0 : Register 19 ................................................................................................7-13
Map Table Register 1 : Register 20 ................................................................................................7-13
Analog Control Register 0 : Register 21 .........................................................................................7-14
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Table of Contents
PRELIMINARY SPECIFICATION
KS8910 100/10 Mbps ETHERNET CONTROLLER
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Table of Contents
