REGISTERS
REGISTER DEFINITIONS
Register
BMCR
BMSR
PHYIDR1
PHYIDR2
ANAR
ANLPAR(BASE PAGE)
ANLPAR(NEXT PAGE)
ANER
ANNPTXR
Reserved
B10CR
TXCR
PAR
MPTBLE0
MPTBLE1
anacr0
anacr1
anasr
B10SR
TXSR
RESERVED
NOTE:
* The addresses given in table 8-1 are in decimal(hex) while they are hexadecimal in the following tables.
* B/E : Basic/Extended
7-2
Table 8-1. Address Mapping
Name
Base Mode Control Register
Base Mode Status Register
PHY Identification Register #1
PHY Identification Register #2
Auto-Negotiation Advertisement
Register
Auto-Negotiation Link Partner
Ability Register
Auto-Negotiation Expansion
Register
Auto-Negotiation Next Page
Transmit Register
-
10Base-T Control Register
100Base_TX Control Register
PHY Address Register
MAP Table Register #0
MAP Table Register #1
Analog Control Register #0
Analog Control Register #1
Analog Status Register
10Base-T Status Register
100Base-TX Status Register
-
KS8910 100/10 Mbps ETHERNET TRANSCEIVER
Address(Hex)
0(00h)
0011_0100_0000_0000
1(01h)
0111_1000_0000_1001
2(02h)
0000_0000_1111_0000
3(03h)
0000_0000_1111_0000
4(04h)
0000_0001_1110_0001
0000_0000_0000_0001
5(05h)
0000_0000_0000_0000
6(07h)
0000_0000_0000_0100
7(07h)
0000_0000_0000_0000
(08h ~ 0fh)
16(10h)
1110_0000_0010_0000
17(11h)
0000_0000_0000_0000
18(12h)
0000_0000_0000_0000
19(13h)
0000_0000_0000_0000
20(14h)
0000_0000_0000_0000
21(15h)
0000_0000_0000_0000
22(16h)
0000_0000_0000_0000
23(17h)
0000_0000_0000_0000
24(18h)
0000_0000_0000_0000
25(19h)
0000_0000_0000_0000
(1a ~ 1fh)
Preliminary Spec. ver
Initial Value
B/E
-
-
1.4
B
B
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E