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100BASE-TX ANALOG BLOCKS
Clock Dividers
The frequency synthesizer is completed by a clock divider circuit that generates the remaining clocks required by
the design. The clocks and their uses are summarized in Table 6-1.
Table 6-1. Transmit Clocks Generated by the Frequency Synthesizer
Clock
clk125
clk25
clk10
clk2.5
clk20
TRANSMIT TWISTED-PAIR DRIVER
The Transmit Twisted-Pair Driver drives current into the transmit transformer. The combination of the driver and the
transformer must meet the ANSI FDDI TP-PMD template specification. External resistors are used to generate a
reference current and to match the driver to the impedance of the twisted-pair transmission line. These external
resistors must have accuracy of ±1%.
A block diagram showing connection of the driver to the transformer is shown in Figure 6-4. The recommended
transformer has a turns ratio of 1(second coil) :
2
(firstcoil)will not enable full 10 Mb/s voltage swing, and higher turns ratios will result in higher power dissipation.
A Pulse ,Valor, XFMRS' s transformer can meet the application requirements.Please refer to "Application Notes".
The 100 Mbit/s driver is connected in parallel with the 10 Mbit/s driver to the TPOP and TPON pins. The chip
automatically switches between the two drivers depending on the state of the autonegotiation circuit and the
Control register (Reg 0). Care should be taken on the board layout to minimize parasitic capacitance and
inductance on traces connecting these pins to the transformer.
The recommand transceiver is Halo Co' s "TG110-S131N2",Pulse Co' s "H001", "H0010", "H1033", "H1035",
"H1095" and Valor Co' s "ST6122", "ST6149".
6-4
100 Mbit/s Transmit Logic
100 Mbit/s MII and Digital
10 Mbit/s Digital
10 Mbit/s MII
10 Mbit/s Analog
2
(first coil). However, turns ratios lower than 1(second coil) :
KS8910 100/10 Mbps ETHERNET TRANSCEIVER
Use
Preliminary Spec. ver
1.4
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