Table of Contents
Advertisement
Preliminary Spec. ver
1.4
KS8910 100/10 Mbps ETHERNET TRANSCEIVER
PHY REGISTERS
BASE MODE CONTROL : REGISTER 0
[BMCR] 00h
15
14
PhyRst
PhyLoop Sp_Sel An_En
•
Col_Test
•
Dup_Mode
•
Re-AN
•
Isolate
•
PD
•
AN_En
•
Sp_Sel
13
12
11
10
PD
Isolate
Collision Test
Duplex Mode
Restart Auto-negotiation
Isolate
Power Down
Auto-negotiation Enable
Speed Selection
9
8
Re_AN
Dup_Mode Col_Test
1 = enable Collision signal test
0 = disable Collision signal test(default)
When set, this bit will cause the COL signal to be asserted in response
to the assertion of TX_EN.
1 = Full Duplex
0 = Half Duplex(default)
Duplex selection is allowed when Auto-negotiation is disabled (bit 12 of
this register is cleared). With Auto-Negotiation enabled, this bit does
not reflects the duplex mode.
1 = Restart Auto-negotiation Process
0 = Normal operation (default)
Re-initiates the Auto-Negotiation process. If Auto-negotiation is Auto-
Negotiation
disabled (bit 12 of this register cleared), this bit has no
function and should be cleared. This bit is self-clearing and will return a
value of 1 until Auto-Negotiation is initiated by KS8925, whereupon it
will self-clear. Operation of the Auto-Negotiation process is not
affected by the management entity clearing this bit.
0 = Normal operation (default)
1 = Internal MII Isolate(High Impedence)
When this bit is set, the PHY Layer does not respond to TXD[3::0],
TX_EN, and TX_ER inputs, and it presents a ' 0 ' on its TX_CLK,
RX_CLK, RX_DV, RX_ER, RXD[3::0], COL and CRS outputs. The
KS8910 still responds to internal management transactions.
1 = Power Down Mode
0 = Normal operation (default)
When this bit is set, PHY blocks goes into power down mode.
1 = Enable Auto-negotiation Process (default)
0 = Disable Auto-negotiation Process
Bit 8 and 13 of this register are ignored when this bit is set. Bit 8 and 13
determine the link speed and mode if this bit is cleared.
1 = 100 Mbit/s
0 = 10 Mbit/s(default)
Sp_Sel Link speed is selected by this bit or by Auto-negotiation
if bit 12 of this register is set. (In which case, the value of this bit
is ignored)
7
6
Reserved
REGISTERS
00h
0
7-3
Advertisement
Table of Contents
