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100BASE-TX ANALOG BLOCKS
The 10Base-T Analog block interfaces the digital logic to the transmit and receive twisted-pair interfaces. A block
diagram of the 10Mbit/s data path is shown in Figure 6-2. The 10Mbit/s digital components are described in
Chapter 5. The analog components are shaded and are described in this chapter.
10Mbit/s Analog Block
100M
10M
100M
10M
The main transmit analog blocks are the clock generator, the wave shaper, and the driver. The receive blocks
include a receive buffer . In addition, the receive circuit detects the presence of on the receive twisted pair and
supplies status signals to the auto-negotiation circuit indicating lock detect and signal detect.
A few external components are required to support the analog circuits. These components include a 25MHz
oscillation circuit and a current reference bias circuit.
100MBIT/S TRANSMIT CIRCUITS
The 100 Mbit/s Transmit analog block generates the clocks required for data transmission and drives the twisted
pair. An on-chip PLL synthesizes a 125 MHz clock from a 25 MHz crystal reference. The 100Base-TX Transmit
Driver provides an output capable of driving a transformer-coupled unshielded twisted pair.
6-2
TXPLL
WAVE SHAPER
RXPLL
DPLL
Figure 6-2. Analog Blocks of KS8910
KS8910 100/10 Mbps ETHERNET TRANSCEIVER
MLT-3
DRIVER
100M
BW EQ
RX EQ
SD
10M
RX SQ
Preliminary Spec. ver
1.4
TPOP
TPON
TPIP
TPIN
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