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Preliminary Spec. ver
1.4
KS8910 100/10 Mbps ETHERNET TRANSCEIVER
Descrambler
The Descrambler shall decode the NRZ cipher-text bit stream from the MLT-3 decoder. The cipher-text bit stream
shall be decoded by addition (modulo 2) of a key stream to produce a plain-text bit stream. The key stream shall be
the periodic sequence of 2047 bits generated by the recursive linear function X[n] = X[n-11] + X[n-9] (modulo 2).
The descrambler shall generate the specified key stream while it is synchronized.
The descrambler is defined to be synchronized while the descrambler key stream added to a sequence of cipher-
text bits is identical to the upstream scrambler key stream added to those bits. While the descrambler is
synchronized, error free bits in the cipher-text stream decode as error free bits in the plain-text stream, and errored
bits in the cipher-text stream decode as errored bits in the plain-text stream.
The descrambler shall acquire synchronization on receipt of 60 consecutive error-free cipher-text bits of the Idle
Line State (ILS) pattern while SIGNAL_DETECT is asserted and the output of the MLT-3 decoder is valid:
In the KS8910, the hybrid mode is supported, the descrambler will, therefore, acquire synchronization on receipt of
30 consecutive error-free cipher-text bits of the JK symbol sequence while SIGNAL_DETECT is asserted and the
output of the MLT-3 decoder is valid.
A functional block diagram of the Descrambler is given in Figure 4-7.
cipher-text
Lock
Acquisition
Figure 4-7. Descramble Function of KS8910
100BASE-TX DIGITAL BLOCKS
LFSR
lfsr_out
plain-text_out
4-11
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