Samsung KS8910 User Manual page 55

Preliminary Spec. ver
1.4
100BASE-TX ANALOG BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER
line termination is performed by the circuit shown in Figure 6-5.
RECEIVE CLOCK RECOVERY(20MHZ,DPLL)
An on-chip frequency synthesis PLL recovers a 20MHz clock using the frequency reference from receiving data.
The PLL uses digital techniques to create the optimum clock for re-timinig the received data.
6-8