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Preliminary Spec. ver
1.4
100BASE-TX ANALOG BLOCKS
KS8910 100/10 Mbps ETHERNET TRANSCEIVER
1 CT
1 CT
TPIP
all resistors are 1%
100Ω
0.1uF
75Ω
0.1uF
TPIN
Chip
Board
Figure 6-5. Receive Buffer Circuit Configuration
ADAPTIVE EQUALIZER
High frequency attenuation and group delay variation introduced by the twisted pair degrades the data signal. The
adaptive equalizer restores these high frequency components and restores the data to a condition suitable for clock
recovery and data slicing.
The signal arriving at the receiver after propagation through a 100 meter unshielded twisted pair exhibits a
completely closed eye diagram. The adaptive equalizer restores this eye to a >90% open state. The equalizer is
capable of restoring data transmitted over cables from 0 meters in length to 125 meters in length.
The adaptive equalizer requires no external filter components and no external user interaction. It is capable of
equalizing NRZ or MTL-3 data.
BASE LINE RESTORE
Baseline wander caused by long run lengths in data is compensated by the baseline restore circuit. Run lengths as
long as 57 bits are possible on 100Base-TX. It is impractical to build transformers that display droop times long
enough to recover data of this run length.
The baseline restore circuit uses a nonlinear signal processing technique to restore data signals that have drooped
due to excessive run lengths.
The circuit also further opens the eye. Residual jitter after equalization and baseline restoration is less than 300 ps.
This decreases the jitter tolerance of the clock recovery circuit.
CLOCK RECOVERY
An on-chip frequency synthesis PLL generates a 125MHz clock from the 25 MHz frequency reference. The Clock
Recovery circuit generates a 125Mhz clock and re-timed data from the equalized signal and The PLL uses a
phase-frequency detector, a charge pump, and integrated voltage controlled oscillator (VCO).
6-6
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