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100BASE-TX DIGITAL BLOCKS
PHYSICAL CODING SUBLAYER (PCS)
The KS8910 PCS maps data and control signals between the MII and PMA. The PCS consists of five functional
blocks as it appears in Figure 4-2.
TxD[3:0]
MII
Tx_en
Tx_er
PCS
TXbits[4:0]
TXbits_en
PMA
In the transmit direction the PCS encodes the data nibbles, received through the MII, into 5-bit code-groups. The
data is, thereupon, serialized and forwarded to the PMA.
In the receive direction data is first deserialized into 5-bit code-groups. This requires that the Parallel Converter has
been able to lock to the incoming data stream which is the case after reception of Start-of-Stream Delimiter, SSD.
The 5-bit code-groups are then decoded into data nibbles which are transferred to the MAC through the MII.
Because of the different wire bit rates of data in parallel form and serial form, two different clocks are required. The
encoding takes place in the 25 MHz clock domain while all other functions require a 125 MHz clock.
A detailed description of each functional block is given the following sub-sections.
4B/5B ENCODER, DECODER
The mapping of the data nibbles into 5-bit code-groups and vice versa is done according to table 24-1 in the IEEE
802-3u standard. Shown at 4B/5B Coding table 4-1 of KS8910.
4-4
Tx_clk
Col
Carrier
Sense
Transmitting
4B/5B
Encoder
Serial
Converter
TX_code-bit
Figure 4-2. PCS Functional Block Diagram of KS8910
KS8910 100/10 Mbps ETHERNET TRANSCEIVER
CrS
Receiving
5B/4B
Decoder
Parallel
Converter
Link_status[1:0]
Preliminary Spec. ver
RxD[3:0]
Rx_DV
Rx_er
Rx_clk
25Mhz
Domain
RXbits[9:0]
RXbits_en
125Mhz
Domain
RX_code-bit
1.4
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